The present invention relates to Power BIMOS applications and, more particularly, to a circuit for clamping the voltage swings possible in an NMOS turn around or differential to single ended converter circuit.
In integrated circuits (IC's) incorporating both bipolar and MOS active devices, it is common (especially in high power applications) to have the substrate of the IC at a high potential with respect to ground potential. Therefore, it is important that the isolated epitaxial regions of the IC, in which the bipolar devices are formed, are not allowed to be at a low voltage with respect to the substrate. If this were allowed to happen a SCR latch would be created due to forward biasing of the substrate-epitaxial junction region. This SCR latch could cause severe damage or even destroy the IC in high power applications.
It is common to use NMOS circuitry because of its high voltage capabilities in conjunction with bipolar devices in integrated circuits. Typically, NMOS circuitry in a BIMOS integrated circuit is utilized to provide control functions. For example, a conventional comparator circuit including a differential bipolar transistor input section can be used in conjunction with an NMOS differential to single ended converter circuit to provide an output signal that changes output level states as the differentially applied input signals vary above and below a predetermined threshold value as is well understood.
However, the above described circuit generally exhibits undesirable large switching delays due to the NMOS transistors. Because of large gate voltage variations in the NMOS differential to single ended converter and the fact that the charging currents at the comparator trip point are small, the switching time delay is dependent on these parameters and the parasitic capacitance of the NMOS devices.
Hence, a need exists for clamping the voltage swing across the output NMOS device of the converter circuit to reduce the switching time delay.